1. Field of the Invention
The present invention relates to a sequence control circuit, in particular to a sequence control circuit to be preferably used in a test pattern generator of a semiconductor memory test apparatus.
2. Description of the Prior Art
A memory test apparatus is used for testing a semiconductor memory device. The memory test apparatus gives an address, data and a control signal to a memory under test (MUT) based on a predetermined test program, that is, a pattern program, and discriminates PASS/FAIL of the MUT by judging whether or not the data then read from the MUT agree with the expectation data at a predetermined timing. When address signals, test data signals and control signals are supplied to the MUT, the expectation data is considered to mean the data to be outputted from the normal MUT corresponding to a combination of the above address signals, test data signals and control signals.
FIG. 1 is a block diagram showing a basic whole structure of a conventional memory test apparatus which has been used. The memory test apparatus 1 performs a test of MUT 2 and comprises: a timing generator 5 for generating a reference clock; a test pattern generator 6 for generating address signals, test data signals and control signals to be given to the MUT 2 by receiving the reference clock; a waveform shaper 7 for receiving the respective signals from the test pattern generator 6 and applying these signals to the MUT 2 after shaping them into waveforms required for the test; and a logic comparator 8 for receiving the data read from the MUT 2 and judging PASS/FAIL; of the expectation data.
The test pattern generator 6 produces expectation data in addition to the address signals, test data signals and control signals. The expectation data is supplied to the logic comparator 8 from the test pattern generator 6. The logic comparator 8 compares the expectation data with a data read from MUT 2, performs quality judgment of the MUT according to match/mismatch of the data and outputs the result as a PASS/FAIL signal to the test pattern generator 6. Further, when the logic comparator 8 Compares the output data of the MUT 2 with the expectation data in a specific cycle of test cycles and detects the agreement between the two, the logic comparator 8 outputs a match flag MFLG to the test pattern generator 6. Here, a series of an address, test data and a control signal to be given to the MUT 2 is called as a test pattern.
Now, the test pattern generator 6 has an address generator 11, a test data generator 12 and a control signal generator 13 which generates the address signals, the test data and the control signals to be given to the MUT 2, respectively, and further has a sequence control circuit 10 which controls the address generator 11, the test data generator 12 and the control signal generator 13.
FIG. 2 is a block diagram showing an example of an internal structure of a conventional sequence control circuit.
The sequence control circuit comprises: an instruction memory 121 for storing a test program consisting of a series of instructions for generating a test pattern; a program counter (PC) 122 for designating an address of the instruction memory 121; a stack register 123 for temporary saving of addresses; a program counter controller 124 for controlling the program counter 122 and the stack register 123; a starting address register (STA) 125 for storing an initial value of the program counter 122; a branch address register (BAR) 126 for storing an address of a branch designated by branch instructions; an index register 127; an index work register 128; and an index counter 129. The index register 127, the index work register 128 and the index counter 129 are all for controlling loop instructions.
Every one of instructions to be stored in the instruction memory 121 is composed of an operation code part, that is, an operation code part of a sequence control instruction, and an operand corresponding to each instruction code. Corresponding to these instructions, the instruction memory 121 has a pair of a sequence control instruction area for storing the operation code part and an operand storing area for storing the operand. In case of a sequence control circuit of this type, there is an operand of a type which expresses a designated branch address or loop conditions in a test program or of a type which describes a parameter for generating an address, test data and a control signal to be given to the MUT 2. Accordingly, this sequence control circuit has, in addition to the above sequence control instruction area, an address operation area, a data operation area and a control, signal generation instruction area provided in a memory area of each address of instruction memory 121. The address operation area, the data operation area and the control signal generation instruction area are provided in the operand storing area.
When the instruction memory 121 is accessed by the address outputted from the program counter 122, instructions for address generation, test data generation and control signal generation are read from the address operation area, the data operation area and the control signal generation instruction area and then supplied to the address generator 11 (FIG. 1), the test data generator 12 (FIG. 1) and the control signal generator 13 (FIG. 1), respectively. Thus, the address generator 11, the test data generator 12 and the control signal generator 13 generate an address, test data and a control signal for the MUT 2, respectively.
The program counter controller 124 receives an operation code part of sequence control instructions from the instruction memory 121, a match flag MFLG from the logic comparator 8 (FIG. 1) and an output of the index counter 129. Based on the result obtained by decoding the instruction stored in the instruction memory 121, on the match flag MFLG, and on an output from the index counter 129, the program counter controller 124 controls the program counter 122 and the stack register 123. In the concrete, the program counter controller 124 handles a content of the program counter 122, that is, the value showing an address to be read next in the instruction memory 121, through increment, decrement or hold operation, and loads the value to the program counter 122. For loading the above value to the program counter 122, the program counter controller 124 arranges corresponding to the instructions read out so that any one of (i) an operand of instructions for a present address of the instruction memory 121, (ii) a content of the starting address register 125, (iii) a content of the branch address register 126, and (iv) a content of the stack register 123 is set to the program counter 122 as the value.
An address read from the operand storing area of the instruction memory 121 is also supplied to the index register 127. The index counter 129 controls loop instructions by using this index register 127 and the index work register 128 which serves as a work register, and when the counter value coincides with a specific value, outputs the value to the program counter controller 124 thereby controlling the program counter 122.
Now in recent years, a semiconductor memory called a flash memory has been developed and manufactured. The flash memory has a merit that it is a non-volatile memory and hence it can hold memory data without particular power supply from outside and can rewrite data stored in the memory in a state as it mounted on a printed wiring substrate. Characteristics of the operation of the flash memory are summarized in the following six items.
(1) operation mode setting by command input,
(2) automatic write,
(3) automatic erase (chip erase/block erase),
(4) detection of data write completion/erase completion,
(5) block protection function,
(6) device code.
Therefore, it is possible to set automatic erasing activity to be performed by a chip unit or a block unit in the flash memory by command input. However, with the flash memory, erasable number of times for the block unit is limited within a certain value while having a probability of breaking down a device due to excess erasing. Therefore, it is necessary to detect the state which informs of write completion/erase completion. In a test pattern for performing a flash memory test, according to a detection result, which is a flag, with reference to a write completion/erase completion state, it switches the branch address of the program counter in the sequence control circuit.
As described above, when the flash memory test is performed, it is required to switch the branch address in the sequence control circuit corresponding to the state of a flag. In the conventional sequence control circuit described above, it is possible to switch the branch address by an indication of one flag. However, when the branch address is switched according to a, combination of a plurality of flag values detected from the flash memory, for example, when the branch address of the pattern program is switched according to contents of both flags, one flag showing execution or termination of automatic algorithm and the other flag showing time limit over, with the conventional sequence control circuit described above, it is impossible to describe switching of the branch address like this only with one statement in the test program.
A first object of the present invention is to provide a sequence control circuit which can designate in a program description a plurality of branches depending on plural branch conditions, thereby enabling a user to describe the program easily.
A second object of the present invention is to provide a sequence control circuit which can designate in a test pattern program description of a semiconductor memory a plurality of branches depending on plural branch conditions, thereby enabling a user to describe the pattern program easily and to reduce the test time. In the concrete, the second object of the present invention is to provide, when contents of signals outputted from a device under test is applied as a branch condition, a sequence control circuit which allows to designate a plurality of branches according to a combination of plural branch conditions.
The first object of the present invention is achieved by a sequence control circuit which has a program counter and in which circuit an address to be loaded to the program counter can be switched depending on the result of detection made for combinations of a plurality of branch conditions.
The second object of the present invention is achieved by a sequence control circuit provided in a test pattern generator of a memory test apparatus for performing a test of a semiconductor memory device, the sequence control circuit comprising an instruction memory for storing each of the instructions of the test program, a plurality of branch address registers each for storing a branch address, a logic operation circuit for receiving a plurality of flags and detecting a combination of flag values, a program counter for outputting an address to the instruction memory, a program counter controller for controlling the program counter according to a control word read from the instruction memory and selecting one of the branch address registers corresponding to a combination of the flag values, wherein the branch address stored in the branch address register selected by the program counter controller is loaded in the program counter.
In other words, in the sequence control circuit of the present invention, according to the detection result of a combination of a plurality of flags which represent branch conditions, the address to be loaded into the program counter is switched. Therefore, by employing the sequence control circuit in the pattern generator of the memory test apparatus for performing the semiconductor memory test, a complicated test pattern can easily be produced through a relatively simple modification of the circuit.
When a time-out occurs during block erasing operation in a flash memory test, the flash memory has been considered defective as it is in the test according to the conventional test pattern, however, in this case, the memory is good and usable in the blocks other than the block showing the time-out. Therefore, it is only necessary to jump to any other block to continue the test without merely discarding the useful memory as defective. According to the sequence control circuit of the present invention, it is particularly easy to generate the test pattern in these cases.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate an example of a preferred embodiment of the present invention.